1999 imp, inc. 408-432-9100/www.impweb.com 1 key features applications u pagers u cellular/gsm/phs phones u instrumentation u wireless terminals u battery powered systems u medical instruments u linear post-regulators u pin compatible with telcom t c1014/1015/1185 u lower dropout voltage for long battery life ?imp2014: 70mv vs. telcom tc 1014 120mv ?imp2015: 160mv vs. telcom tc 1015 250mv ?IMP2185: 250mv vs. telcom tc1185 400mv u power saving shutdown mode ?0.2? shutdown current u superior load regulation ?0.32% u long battery life ?33? no load ground current u accurate output voltage ? 2.5% over temperature u low drift output: 40ppm/ c u guaranteed minimum output current ?imp2014: 60ma ?imp2015: 110ma ?IMP2185: 160ma u over-current and over-temperature protection u reference bypass input for low-noise and improved psrr u compact sot-23a-5 package imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 p ower m anagement 60ma/1 60ma/1 1 1 0ma/1 0ma/1 60ma 60ma super lo super lo w dr w dr opout cmos opout cmos r r egulat egulat or or s wit s wit h batt h batt er er y lif y lif e e ext ext ending shutdo ending shutdo wn mode wn mode the imp2014, imp2015 and IMP2185 high performance cmos low dropout voltage regulators offer superior dropout voltage performance and load regulation characteristics as compared to the pin compatible tc1014/1015/1185 devices offered by telcom semiconductor. dropout voltage performance has been improved by up to 40%. load regulation and power supply psrr have been optimized. load regulation is typically 0.32% and psrr is 53db at 1khz. a logic input controlled shutdown mode extends system battery life by reducing quiescent current to 0.2 m a maximum. the shutdown mode can be initiated by a system microcontroller. the regulators were designed with ease of use and stability in mind. stability is guaranteed for 0.47 m f and greater load capacitors with an esr up to 5 w . ceramic or tantalum capacitors can be used. three devices with different guaranteed output current specifications are available: imp2014 (60ma), imp2015 (110ma) and IMP2185 (160ma). each device has output voltage options of 2.5v, 2.7v, 2.85v, 3.0v, 3.3v, 3.6v and 4.0v. typical application 0.01 m f/3.3 m f (optional) 1 m f1 m f + v in v out imp2014 imp2015 IMP2185 bypass shutdown* control 1 3 5 4 2 shdn 2014/15_02.eps gnd v out * tie to v in if not used.
2 408-432-9100/www .impweb.com 1999 imp , inc. imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 imp20 1 4 / 1 5 IMP2185 v in shdn 1 v out 5 3 byp ass 4 gnd 2 2014/15_01.eps so t -23a * r e b m u n t r a p e g a k c a p t u p t u o e g a t l o v ) v ( t u p t u o t n e r r u c ) a m ( n w o d t u h s n i p t s u j d a n i p y a k o g a l f t u p t u o e c n e r e f e r n i p s s a p y b g n i k r a m e g a k c a p a b c d t / k u j 5 . 2 - 4 1 0 2 p m i 5 - a 3 2 t o s 5 . 2 0 6 l l m a x x t / k u j 7 . 2 - 4 1 0 2 p m i 5 - a 3 2 t o s 7 . 2 0 6 l l m b x x t / k u j 5 8 . 2 - 4 1 0 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 6 l l m c x x t / k u j 0 . 3 - 4 1 0 2 p m i 5 - a 3 2 t o s 0 . 3 0 6 l l m d x x t / k u j 3 . 3 - 4 1 0 2 p m i 5 - a 3 2 t o s 3 . 3 0 6 l l m e x x t / k u j 6 . 3 - 4 1 0 2 p m i 5 - a 3 2 t o s 6 . 3 0 6 l l m f x x t / k u j 0 . 4 - 4 1 0 2 p m i 5 - a 3 2 t o s 0 . 4 0 6 l l m g x x t / k u j 5 . 2 - 5 1 0 2 p m i 5 - a 3 2 t o s 5 . 2 0 1 1 l l o a x x t / k u j 7 . 2 - 5 1 0 2 p m i 5 - a 3 2 t o s 7 . 2 0 1 1 l l o b x x t / k u j 5 8 . 2 - 5 1 0 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 1 1 l l o c x x t / k u j 0 . 3 - 5 1 0 2 p m i 5 - a 3 2 t o s 0 . 3 0 1 1 l l o d x x t / k u j 3 . 3 - 5 1 0 2 p m i 5 - a 3 2 t o s 3 . 3 0 1 1 l l o e x x t / k u j 6 . 3 - 5 1 0 2 p m i 5 - a 3 2 t o s 6 . 3 0 1 1 l l o f x x t / k u j 0 . 4 - 5 1 0 2 p m i 5 - a 3 2 t o s 0 . 4 0 1 1 l l o g x x t / k u j 5 . 2 - 5 8 1 2 p m i 5 - a 3 2 t o s 5 . 2 0 6 1 l l x a x x t / k u j 7 . 2 - 5 8 1 2 p m i 5 - a 3 2 t o s 7 . 2 0 6 1 l l x b x x t / k u j 5 8 . 2 - 5 8 1 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 6 1 l l x c x x t / k u j 0 . 3 - 5 8 1 2 p m i 5 - a 3 2 t o s 0 . 3 0 6 1 l l x d x x t / k u j 3 . 3 - 5 8 1 2 p m i 5 - a 3 2 t o s 3 . 3 0 6 1 l l x e x x t / k u j 6 . 3 - 5 8 1 2 p m i 5 - a 3 2 t o s 6 . 3 0 6 1 l l x f x x t / k u j 0 . 4 - 5 8 1 2 p m i 5 - a 3 2 t o s 0 . 4 0 6 1 l l x g x x l e e r d n a e p a t s e t a c i d n i t / * e d o c e t a d = x x s p e . 3 0 t _ 5 1 / 4 1 0 2 r e b m u n n i p e m a n n o i t c n u f 1 v n i . t u p n i y l p p u s d e t a l u g e r n u 2 d n g . l a n i m r e t d n u o r g 3 n d h s g n i r u d . w o l c i g o l a s i n d h s n e h w d e r e t n e s i e d o m n w o d t u h s a . t u p n i l o r t n o c n w o d t u h s 0 . 2 o t s p o r d t n e r r u c t n e c s e i u q d n a v 0 o t s l l a f e g a t l o v t u p t u o e h t n w o d t u h s m . a 4 s s a p y b s e c u d e r d n u o r g o t n i p s s a p y b e h t m o r f d e t c e n n o c r o t i c a p a c a . t u p n i s s a p y b e c n e r e f e r r r s p s e c n a h n e d n a e c n e r e f e r l a n r e t n i e h t n o t n e s e r p e s i o n e h t 5 v t u o e g a t l o v t u p t u o s p e . 1 0 t _ 5 1 / 4 1 0 2 pin configuration pin descriptions ordering infor mation
1999 imp , inc. 408-432-9100/www .impweb.com 3 imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 input v oltage . . . . . . . . . . . . . . . . . . . . . . . . . 7v output v oltage . . . . . . . . . . . . . . . . . . . . . . . . 0.3v to v in + 0.3v maximum v oltage on any pin . . . . . . . . . . . . 0.3v to (v in + 0.3v) shutdown v oltage (shdn) . . . . . . . . . . . . . . shdn v in + 0.3v operating junction t emperatur e range . . . 40 c < t j < 125 c storage t emperatur e . . . . . . . . . . . . . . . . . . . 65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . internally limited note: t j = junction t emperatur e, t a = ambient t emperatur e these ar e str ess ratings only and functional operation is not implied. exposur e to absolute maximum ratings for pr olonged time periods may affect device r eliability . all voltages ar e with r espect to gr ound. v in = v out +1v , i l = 100 m a, c l = 1 m f , shdn > v i h , t a = 25 c, unless otherwise noted. bold/ blue specifications apply for junction temperatur e range 40 c < t j < 125 c. notes: 1. v r is the r egulated output voltage: 2.5v , 2.7v , 2.85v , 3.0v , 3.3v , 3.6v or 4.0v . 2. dr opout v oltage is defined as the differ ence between in and out when v r dr ops 2% below its nominal value. 3. specifications which would otherwise be affected by self-heating of the die ar e tested at a constant die temperatur e by using low duty cycle pulse testing. 3. psrr guaranteed by design. r e t e m a r a p l o b m y s s n o i t i d n o c n i m p y t x a m s t i n u e g n a r e g a t l o v t u p n i v n i 0 c t < j 5 2 1 < c 0 5 . 6 v 0 4 c t < j 5 2 1 < c 0 5 . 6 t n e r r u c t u p t u o m u m i x a m i x a m o 4 1 0 2 p m i 0 6 a m 5 1 0 2 p m i 0 1 1 5 8 1 2 p m i 0 6 1 e g a t l o v t u p t u o d e x i f v t u o 1 e t o n v r % 5 . 2 v r % 5 . 0 v r % 5 . 2 + v ) 2 e t o n ( e g a t l o v t u o p o r d v n i v - o i l 0 0 1 = m a 1 v m i l a m 0 2 = 7 1 3 2 i l a m 0 5 = 0 6 0 7 i l ) 5 8 1 2 p m i , 5 1 0 2 p m i ( a m 0 0 1 = 0 9 0 6 1 i l ) 5 8 1 2 p m i ( a m 0 5 1 = 3 4 1 0 5 2 t n e r r u c t n e c s e i u q ) t n e r r u c d n u o r g ( d a o l o n 3 3 0 5 m a t n e r r u c y l p p u s n w o d t u h s i d s n i v 0 = n d h s t j 5 2 c 2 . 0 2 m a t n e i c i f f e o c e r u t a r e p m e t t u p t u o 0 4 m p p / c n o i t a l u g e r l a m r e h t 4 0 . 0 w / % n o i t a l u g e r e n i l v r v 1 + v n i v 6 5 7 3 0 . 0 5 3 . 0 % s p e . a 2 0 t _ 5 1 / 4 1 0 2 absolute maximum ratings electrical characteristics
4 408-432-9100/www .impweb.com 1999 imp , inc. imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 v in = v out +1v , i l = 100 m a, c l = 1 m f , shdn > v i h , t a = 25 c, unless otherwise noted. bold/ blue specifications apply for junction temperatur e range of 40 c < t j < 125 c. notes: 1. v r is the r egulated output voltage: 2.5v , 2.7v , 2.85v , 3.0v , 3.3v , 3.6v or 4.0v . 2. dr opout v oltage is defined as the differ ence between in and out when v r dr ops 2% below its nominal value. 3. specifications which would otherwise be affected by self-heating of the die ar e tested at a constant die temperatur e by using low duty cycle pulse testing. 4. psrr guaranteed by design. r e t e m a r a p l o b m y s s n o i t i d n o c n i m p y t x a m s t i n u : n o i t a l u g e r d a o l 4 1 0 2 p m i i l 0 0 1 = m a m 0 5 o t a 1 1 . 0 5 . 0 % 5 1 0 2 p m i i l 0 0 1 = m a m 0 0 1 o t a 6 1 . 0 0 . 1 5 8 1 2 p m i i l 0 0 1 = m a m 0 5 1 o t a 5 6 . 0 5 . 1 e i d n w o d t u h s l a m r e h t e r u t a r e p m e t 0 5 1 c s i s e r e t s y h n w o d t u h s l a m r e h t 2 1 c n o i t c e j e r e l p p i r r r s p v n i 3 v ( o ) v 1 + v 5 2 . 0 c o 3 . 3 = m c i m a r e c f c s s a p y b 1 0 . 0 = m f = . q e r f z h k 1 0 6 b d = . q e r f z h k 0 1 7 4 = . q e r f z h m 1 4 3 e s i o n t u p t u o z h k 0 5 o t z h 0 0 3 r o t i c a p a c s s a p y b o n i l ) 4 1 0 2 p m i ( a m 0 5 = i l a m 0 0 1 = 0 8 2 m v s m r z h k 0 5 o t z h 0 0 3 c s s a p y b 1 0 . 0 = m f i l ) 4 1 0 2 p m i ( a m 0 5 = i l a m 0 0 1 = 0 6 m v s m r d l o h s e r h t h g i h t u p n i n d h s v 5 . 2 v n i v 5 . 6 5 4 v f o % n i d l o h s e r h t w o l t u p n i n d h s v 5 . 2 v n i v 5 . 6 5 1 v f o % n i v o t n i t n e r r u c e s r e v e r t u o v ) n i ( v < ) t u o ( v = h g i h = n d h s n i 0 . 2 a m v ) n i ( v < ) t u o ( w o l = n d h s 7 . 2 m a t i m i l t n e r r u c t u p t u o 0 5 3 0 0 6 a m s p e . b 2 0 t _ 5 1 / 4 1 0 2 electrical characteristics
imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 t ypical characteristics 1999 imp , inc. 408-432-9100/www .impweb.com 5 figur e 1. line t ransient response figur e 2. enable input response v o u t 2 0 1 4 / 1 5 _ 1 2 . e p s 5 0 m v / d i v 2 0 m s / d i v d v i n = 1 v 0 v o u t p u t 2 0 1 4 / 1 5 _ 1 3 . e p s 1 v / d i v 5 v / d i v 1 0 0 m s / d i v 0 v e n a b l e figur e 3. load t ransient response (50ma step) figur e 4. load t ransient response (100ma step) v o u t 2 0 1 4 / 1 5 _ 0 9 . e p s 2 5 m v / d i v 2 0 m a / d i v 5 0 m s / d i v l o a d p u l s e v o u t 2 0 1 4 / 1 5 _ 1 0 . e p s 2 5 m v / d i v 5 0 m a / d i v 5 0 m s / d i v l o a d p u l s e figur e 5. output short cir cuit response 2 0 1 4 / 1 5 _ 1 1 . e p s 1 0 0 m a / d i v 1 0 0 m s / d i v
imp20 imp20 1 1 4/1 4/1 5, imp2 5, imp2 1 1 85 85 application infor mation 6 408-432-9100/www .impweb.com 1999 imp , inc. the imp2014, imp2015 and IMP2185 have been designed to of fer exceptionally low dr opout voltage, superior load r egulation and minimum quiescent power . shutdown mode a battery-life-extending mode is available. thr ough the active low shutdown pin, shdn, the r egulator can be enabled or turned of f. the r egulator is shutdown (turned of f) when shdn is low and enabled (turned on) when shdn is high. the shutdown signal can be supplied fr om a cmos gate or fr om an i/o port of a micr ocontr oller . during shutdown, the output voltage falls to 0v and the supply curr ent is typically only 200na. if the shutdown mode is not needed, shdn should be connected dir ectly to the r egulator input voltage pin. output capacitor the imp2014, imp2015 and IMP2185 wer e designed for stable operation with a wide range of capacitor values and type. the output capacitor should be above 0.47 m f . a 1 m f value is r ecom - mended. ceramic or tantalum capacitors ar e suitable with an esr of up to 5 w . reference v oltage bypass capacitor for low noise operation a 0.01 m f or lar ger capacitor can be con - nected fr om the byp ass pin to gr ound. for maximum power sup - ply r ejection/line r ejection, a 3.3 m f value is suggested. the imp2014/2015/2185 wer e designed so that line r egulation and ripple r ejection would be maximized. this was accomplished by powering the internal bandgap r efer ence fr om an internal r eg - ulated sour ce. this "pr e-r egulation" gr eatly impr oves power sup - ply r egulation for input voltages gr eater than that of the internal voltage r egulator , 3.5v . ther mal shutdown an on-chip thermal pr otection cir cuit shuts the ldo r egulator of f when the die temperatur e exceeds 150 c. ther e is a built in 12 c hyster esis. the r egulator will r emain of f until the die temperatur e dr ops to appr oximately to 138 c.
|
